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rail-to-rail, fast, low power 2.5 v to 5.5 v, single-supply ttl/cmos comparator adcmp608 features functional block diagram adcmp608 noninverting input inverting input q output + ? s dn 06769-001 fully specified rail to rail at v cc = 2.5 v to 5.5 v input common-mode voltage from ?0.2 v to v cc + 0.2 v low glitch cmos-/ttl-compatible output stage 40 ns propagation delay low power: 1 mw at 2.5 v shutdown pin power supply rejection > 60 db ?40c to +125c operation figure 1. applications high speed instrumentation clock and data signal restoration logic level shifting or translation high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry pulse-width modulators current-/voltage-controlled oscillators general description the adcmp608 is a fast comparator fabricated on xfcb2, an analog devices, inc. proprietary process. this comparator is exceptionally versatile and easy to use. features include an input range from v ee ? 0.2 v to v cc + 0.2 v, low noise, ttl-/cmos- compatible output drivers, and shutdown inputs. the device offers 40 ns propagation delays driving a 15 pf load with 10 mv overdrive on 500 a typical supply current. the ttl-/cmos-compatible output stage is designed to drive up to 15 pf with full rated timing specifications and to degrade in a graceful and linear fashion as additional capacitance is added. the input stage of the comparator offers robust protec- tion against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. the adcmp608 is available in a tiny 6-lead sc70 package with a single-ended output and a shutdown pin. a flexible power supply scheme allows the device to operate with a single +2.5 v positive supply and a ?0.2 v to + 2.7 v input signal range up to a +5.5 v positive supply with a ?0.2 v to +5.7 v input signal range. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved.
adcmp608 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 absolute maximum ratings............................................................ 4 thermal resistance ...................................................................... 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 6 application information...................................................................7 power/ground layout and bypassing........................................7 ttl-/cmos-compatible output stage ....................................7 optimizing performance..............................................................7 comparator propagation delay dispersion ..............................7 crossover bias point .....................................................................8 minimum input slew rate requirement ...................................8 typical application circuits ............................................................9 outline dimensions ....................................................................... 10 ordering guide .......................................................................... 10 revision history 4/07revision 0: initial version
adcmp608 rev. 0 | page 3 of 12 specifications electrical characteristics v cc = 2.5 v, t a = ?40c to +125c. typical values are t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit dc input characteristics voltage range v p , v n v cc = 2.5 v to 5.5 v ?0.2 v cc v common-mode range v cc = 2.5 v to 5.5 v ?0.2 v cc v differential voltage v cc = 2.5 v to 5.5 v v cc v offset voltage v os ?5.0 3 +5.0 mv bias current i p , i n ?0.4 +0.4 a offset current ?1.0 +1.0 a capacitance c p , c n 1 pf resistance, differential mode ?0.5 v to v cc + 0.5 v 200 7000 k resistance, common mode ?0.5 v to v cc + 0.5 v 100 4000 k active gain a v 80 db v cc = 2.5 v, v cm = ?0.2 v to 2.7 v 45 db common-mode rejection cmrr v cc = 5.5 v 45 db shutdown pin characteristics 1 v ih comparator is operating 2.0 v cc v v il shutdown guaranteed ?0.2 +0.4 +0.4 v i ih v ih = v cc ?6 +6 a sleep time t sd l cc < 100 a 300 ns wake-up time t h v pp = 10 mv, output valid 150 ns dc output characteristics v cc = 2.5 v to 5.5 v output voltage high level v oh i oh = 0.8 ma, v cc = 2.5 v v cc ? 0.4 v output voltage low level v ol i ol = 0.8 ma, v cc = 2.5 v 0.4 v ac performance 2 v cc = 2.5 v to 5.5 v rise time/fall time t r , t f 10% to 90%, v cc = 2.5 v 25 to 50 ns 10% to 90%, v cc = 5.5 v 45 to 75 ns propagation delay t pd v od = 10 mv, v cc = 2.5 v 30 to 50 ns v od = 50 mv, v cc = 5.5 v 35 to 60 ns propagation delay skewrising to falling transition v cc = 2.5 v v cc = 5.5 v 4.5 8 ns ns overdrive dispersion 10 mv < v od < 125 mv 12 ns common-mode dispersion ?0.2 v < v cm < v cc + 0.2 v 1.5 ns p o w e r s u p p l y supply voltage range v cc 2.5 5.5 v positive supply current i vcc v cc = 2.5 v 550 800 a v cc = 5.5 v 800 1300 a power dissipation p d v cc = 2.5 v 1.375 2.0 mw v cc = 5.5 v 4.95 7.15 mw power supply rejection ratio psrr v cc = 2.5 v to 5.5 v ?50 db shutdown current i sd v cc = 2.5 v to 5.5 v 250 350 a 1 the output will be in a high impedance mode when the device is in shutdown mode. note that this feature should be used with ca re since the enable/disable time is much longer than with a true tristate output. 2 v in = 100 mv square input at 1 mhz, v cm = 0 v, cl = 15 pf, v cci = 2.5 v, unless otherwise noted.
adcmp608 rev. 0 | page 4 of 12 absolute maximum ratings table 2. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltages ?0.5 v to +6.0 v supply voltage (v cc to gnd) supply differential ?6.0 v to +6.0 v input voltages input voltage ?0.5 v to v cc + 0.5 v thermal resistance differential input voltage (v cc + 0.5 v) ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. maximum input/output current 50 ma shutdown control pin applied voltage (s dn to gnd) ?0.5 v to v cc + 0.5 v table 3. thermal resistance maximum input/output current 50 ma package type ja 1 unit output current 50 ma adcmp608 6-lead sc70 426 c/w temperature 1 measurement in still air. operating temperature, ambient ?40c to +125c esd caution operating temperature, junction 150c
adcmp608 rev. 0 | page 5 of 12 pin configuration and fu nction descriptions adcmp608 top view (not to scale) q 1 v cc 6 v ee 2 s dn 5 v p 3 v n 4 06769-002 figure 2. pin configuration table 4. adcmp608 pin function descriptions pin no. mnemonic description 1 q noninverting output. q is at logic high if th e analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n . 2 v ee negative supply voltage. 3 v p noninverting analog input. 4 v n inverting analog input. 5 s dn shutdown. drive this pin low to shut down the device. 6 v cc v cc supply.
adcmp608 rev. 0 | page 6 of 12 typical performance characteristics v cc =2.5 v, t a = 25c, unless otherwise noted. 0.5 1.0 1.5 2.0 2.5 3.0 38.0 37.8 37.6 37.4 37.2 37.0 36.8 36.6 36.4 36.2 36.0 propagation delay (ns) v cm at v cc (2.5v) propagation delay rise propagation delay fall 06769-006 3.53.02.52.01.51.00.5 0 ?0.5 ?1.0 v cm at v cc (2.5v) 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 i b (a) +125c ?40c +25c 06769-003 figure 3. input bias current vs. input common-mode voltage figure 6. propagation delay vs. input common-mode voltage 150 100 50 0 od (mv) 60 55 50 45 40 35 30 25 20 t pd (ns) v cc = 5.5v rise delay v cc = 5.5v fall delay v cc = 2.5v rise delay v cc = 2.5v fall delay 06769-004 q 0.5v/div 10ns/div 06769-007 figure 7. 1 mhz output voltage waveform v cc = 2.5 v figure 4. propagation delay vs. input overdrive at v cc = 2.5 v and 5.5 v 1v/div 10ns/div q 06769-008 4.0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 1.0 0.5 0 ?0.5 ?1.0 load current (ma) v out (v) sink source 06769-005 figure 8. 1 mhz output voltage waveform v cc = 5.5 v figure 5. load current (ma) vs. v oh /v ol
adcmp608 rev. 0 | page 7 of 12 application information output q2 q1 +in ?in output stage v logic gain stage a2 a1 a v 06769-009 power/ground layout and bypassing the adcmp608 comparator is a high speed device. despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. of critical importance is the use of low impedance supply planes, particularly the output supply plane (v cc ) and the ground plane (gnd). individual supply planes are recommended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. a 0.1 f bypass capacitor should be placed as close as possible to the v cc supply pin. the capacitor should be connected to the gnd plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the v cc pin. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. figure 9. simplified schematic diagram of ttl-/cmos-compatible output stage optimizing performance as with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. stray capacitance, inductance, common power and ground impedances, or other layout issues can severely limit performance and can often cause oscillation. the source impedance should be minimized as much as is practicable. high source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. higher impedances encourage undesired coupling. ttl-/cmos-compatible output stage specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. the output of the adcmp608 is designed to directly drive one schottky ttl, or three low power schottky ttl loads, or the equivalent. for large fan outs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. comparator propagation delay dispersion the adcmp608 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mv to v cc C 1 v. propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). with the rated 15 pf load capacitance applied, more than half of the total device propagation delay is output stage slew time. because of this, the total propagation delay decreases as v cc decreases, and instability in the power supply may appear as excess delay dispersion. propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instru- mentation. it is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed ( delay is measured to the 50% point for whatever supply is in use; thus, the fastest times are observed with the v cc supply at 2.5 v, and larger values are observed when driving loads that switch at other levels. overdrive and input slew rate dispersions are not significantly affected by output loading and v cc variations. figure 10 and figure 11 ). the ttl-/cmos-compatible output stage is shown in the simplified schematic diagram (see adcmp608 dispersion is typically < 12 ns as the overdrive varies from 10 mv to 125 mv. this specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negative- going inputs, and very low output skews. remember to add the actual device offset to the overdrive for repeatable dispersion measurements. figure 9 ). because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads.
adcmp608 rev. 0 | page 8 of 12 q output input voltage 500mv overdrive 10mv overdrive dispersion v n v os 06769-010 crossover bias point rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. certain devices are active near the v cc rail and others are active near the v ee rail. at some predeter- mined point in the common-mode range, a crossover occurs. at this point, normally v cc /2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. the adcmp608 slightly elaborates on this scheme. crossover points can be found at approximately 0.8 v and 1.6 v. figure 10. propagation delayoverdrive dispersion minimum input slew rate requirement with the rated load capacitance and normal good pc board design practice, as discussed in the q output input voltage 10v/ns 1v/ns dispersion v n v os 06769-011 optimizing performance section, these comparators should be stable at any input slew rate with no hysteresis. broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. with additional capacitive loading or poor bypassing, oscillation may be encountered. these oscilla- tions are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and pc board. in many applications, chattering is not harmful. figure 11. propagation delayslew rate dispersion
adcmp608 rev. 0 | page 9 of 12 typical application circuits adcmp608 output 0.1f 2.5v to 5 v 0.1f 2k ? 2k ? input 06769-012 figure 12. self-biased, 50% slicer adcmp608 cmos v cc 2.5v to 5v 100 ? lvds output 06769-013 figure 13. lvds-to-cmos receiver
adcmp608 rev. 0 | page 10 of 12 outline dimensions compliant to jedec standards mo-203-ab 0.22 0.08 0.30 0.15 1.00 0.90 0.70 seating plane 4 5 6 3 2 1 pin 1 0.65 bsc 1.30 bsc 0.10 max 0.10 coplanarity 0.40 0.10 1.10 0.80 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.46 0.36 0.26 figure 14. 6-lead thin shrink small outline transistor package (sc70) (ks-6) dimensions shown in millimeters ordering guide temperature range package option model package description branding ADCMP608BKSZ-R2 ?40c to +125c 6-lead thin shrink small o utline transistor package (sc70) ks-6 g0u 1 adcmp608bksz-rl ?40c to +125c 6-lead thin shrink small o utline transistor package (sc70) ks-6 g0u 1 adcmp608bksz-reel7 ?40c to +125c 6-lead thin shrink small o utline transistor package (sc70) ks-6 g0u 1 1 z = rohs compliant part.
adcmp608 rev. 0 | page 11 of 12 notes
adcmp608 rev. 0 | page 12 of 12 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06769-0-4/07(0)

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